The present disclosure relates to semiconductor structures and methods of fabricating the same. More particularly, the present disclosure relates to semiconductor structures including parallel graphene nanoribbons or carbon nanotubes, which can be used as device channels, oriented along crystallographic directions. The present disclosure also relates to methods of making such semiconductor structures in which the graphene nanoribbons or carbon nanotubes are fabricated from a template of silicon carbide (SiC) fins or nanowires.
In the semiconductor industry there is a continuing trend toward fabricating integrated circuits (ICs) with higher densities. To achieve higher densities, there has been, and continues to be, efforts toward down scaling the dimensions of the devices on semiconductor wafers generally produced from bulk silicon or silicon-on-insulator (SOI). These trends are pushing the current technology to its limits.
Very Large Scale Integrated (VLSI) circuits are typically realized with Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). As the length of the MOSFET gate is reduced, there is a need to thin the SOI body (channel) so the device maintains good short channel characteristics. Adding a second gate opposite the first gate, so the channel is controlled from both opposite faces of the SOI body allows additional scaling of the gate length. The best short channel control is achieved when a gate-all-around the channel is used.
In view of the above, the semiconductor industry is pursuing graphene to achieve some of the aforementioned goals. Graphene, which is essentially a flat sheet of carbon atoms, is a promising material for radio frequency (RF) transistors and other electronic transistors. Typical RF transistors are made from silicon or more expensive semiconductors such as, for example, indium phosphide (InP). The measured mobility of electrons in graphene was found to be much higher than for InP or for silicon.
With all its excellent electronic properties, graphene is missing a bandgap, making it unsuitable for fabrication of digital devices. Transistors fabricated using graphene in the channel would have Ion/Ioff ratios of the order of 10 or less, with many more orders of magnitude (Ion/Ioff of approximately 106) still required for proper function of such devices. It has been shown that bandgaps can be created in graphene if fabricated in the form of nanoribbons or a closed carbon nanotube (CNT). The size of the bandgap increases with decreasing width of the nanoribbon and for potential practical application the width of the graphene nanoribbons (GNR) has to be less than 10 nm, preferably less than 5 nm.
Fabrication of GNR has been demonstrated before on exfoliated graphene nanoflakes. The prior art for fabrication of GNR is based on patterning and etching, usually by RIE, of the graphene layer. Such techniques form nanoribbons with non-uniform and potentially damaged edges, forming line edge roughness, LER, which deteriorates the electrical quality of the GNR.
CNT field effect transistors are known to have excellent characteristics however accurate placement of the CNTs required for making a very large integrated circuit is very challenging. While some progress has been made by oriented growth of CNTs, the achievable CNT to CNT pitch is of the order of a micron. As a benchmark, present day devices are made with a pitch of 50 nm (0.05 microns).